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FPGA Digital Downconverter

A hardware digital downconverter implemented on a PYNQ-Z1 FPGA to select a frequency channel from a wider-band signal and output filtered baseband I/Q data.

FPGA
SystemVerilog PYNQ-Z1 Vivado Cocotb Python

Simulated multi-channel radio signals are generated in Python and streamed to the FPGA. The FPGA tunes to a selected frequency, shifts the channel to baseband, filters unwanted frequency content, and outputs I/Q samples for further SDR processing.

The project implements one complete and independently testable signal-processing subsystem that can later be integrated into a larger SDR receiver.

The FPGA datapath implements an NCO, complex mixer, and FIR filter to tune to a selected frequency, shift it to baseband, and isolate the desired channel.

Python Test Signal Simulated multi-channel input
↓
ARM Processor Control and sample transfer
AXI DMA ↓
FPGA Digital Downconverter
FIFO/NCO → Complex Mixer → FIR Filter → I/Q Output
AXI DMA ↓
Python Analysis Verify and visualize I/Q output
  • NCO generates the local oscillator based on the selected channel frequency.
  • Complex mixer shifts the selected channel to baseband and produces I/Q samples.
  • FIR filters remove nearby channels and unwanted frequency content.
  • The datapath is built as AXI4-Stream RTL IP with FIFO buffering, AXI DMA, and memory-mapped tuning registers for runtime channel selection.
  • The RTL is tested against Python DSP reference models using Cocotb and Verilator.

The RTL is tested against Python DSP reference models using Cocotb and Verilator, with waveform analysis in GTKWave and implementation analysis in Vivado.

Coming soon.

Coming soon.