FPGA Digital Design

A standard ALU supporting addition, subtraction, multiplication, and squaring with board switch inputs, built from full-adder and multi-bit adder/subtractor modules.

A four-letter Wordle game implemented with an FSM handling guess processing, repeated-letter matching, game state, and win/loss conditions. A testbench covers different gameplay scenarios.

A hardware accelerator for the hyperbolic tangent function using an 11th-degree Taylor approximation and fixed-point arithmetic. The multiplier-adder datapath was pipelined to improve timing performance through throughput, critical-path, and latency analysis.

A matrix-vector multiplication accelerator using 8-lane dot-product units, on-chip memory, and FSM control logic. Designed around a 350 MHz timing target and inspired by the matrix-vector unit used in Microsoft's BrainWave accelerator. A Linux kernel driver to schedule DMA transfers and a Rust userspace runtime to run a multi-layer MLP on the accelerator are in development.

Developing a 32-bit RISC-V processor in Verilog, progressing from a single-cycle datapath to a five-stage fetch, decode, execute, memory, and writeback pipeline. Operand forwarding and hazard detection resolve data and control hazards. The core is simulated in Verilator with waveforms inspected in GTKWave, and verified by running RV32 benchmark programs.